Confusion with component instantiations in VHDL

aijazbaig1 · #1 12-Aug-2006, 03:01

Hello there.
I have a doubt with regards to instantiating components and then linking them to a given entity in VHDL.
This doubt popped up because in my last post I had posted a working program wherein the component wasn't explicitly tied to any given entity. It just had exactly the same name as the entity.
Heres the code to begin with:

Code:

library ieee;
use ieee.std_logic_1164.all;

entity mux is
    port(a,b:IN std_logic_vector(7 downto 0);
        sel:IN std_logic_vector(1 downto 0);
        c : OUT std_logic_vector(7 downto 0));
end mux;

architecture example of mux is
begin
   process(a,b,sel)
   begin
      if(sel = "00") then
      c <= "00000000";
      elsif (sel = "01") then
      c <= a;
      elsif (sel = "10") then
      c <= b;
      else
      c <= (OTHERS => 'Z');
      end if;
   end process;
end example;

----------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity tb_mux is
end entity;

architecture testbench of tb_mux is
signal a,b,c : std_logic_vector(7 downto 0);
signal sel  : std_logic_vector(1 downto 0);
component mux is
   port(a,b : in std_logic_vector(7 downto 0);
        sel : in std_logic_vector(1 downto 0);
        c : out std_logic_vector(7 downto 0));
 end component;

 begin
 M1:mux port map(a,b,sel,c);
 process
 begin
     a <= X"11" after 1 ns,
          X"AF" after 2 ns,
          X"BB" after 3 ns,
          X"6F" after 4 ns;

     b <= X"01" after 1 ns,
          X"2F" after 2 ns,
          X"3C" after 3 ns,
          X"BE" after 4 ns;

     sel <= B"00" after 1 ns,
            B"01" after 2 ns,
            B"10" after 3 ns,
            B"11" after 4 ns;
   wait;
  end process;
end testbench;

If u'd recollect its the same code I posted in my last thread. However I've noticed things about it as I said before which has put me into a dilemma. VHDL says that components are like chip connectors and nothing else. We actually have to link them to entity just as we would solder a chip inside a chip-connector for the latter to do useful work. Now in the program above there isn't a single line which actually links component mux to entity mux. And then it goes on to instantiate a component called M1 based on that. Does it mean that if the names of the entity and the component are exactly the same then they get linked automatically??

Furthermore, when we instantiate component(s) and we would like the ports of the component to get connected to external signals which could be the input/output ports of a higher level entity(see footnote below to see what I mean here by higher level), do we have to place the port names of the entity at the corresponding component ports directly if we are using position based instantiation?

Looking to hear from you,

(By higher level I mean an entity which contains a component inside itself. In terms of structure of the code, it implies that we declare and define a component in the declaration part of an entity. In that case the entity in question is one step 'higher' in terms of hierarchy. I hope you got what I mean here

)

davekw7x · #2 12-Aug-2006, 09:19

Quote:

Originally Posted by aijazbaig1

I have a doubt with regards to instantiating components and then linking them to a given entity in VHDL.

a dilemma

It's a self-made dilemma because you are trying to understand things.

In classes (not just VHDL) instructors sometimes wish that their students would just take their examples (and opinions) and just keep plowing through with the hope that all will become made clear later on. (Sometimes it works out that way; sometimes it doesn't.)

That doesn't mean that the instructors are Bad People; it just means that they have other things to cover, and if they get into a pattern of interrupting the flow in order to answer out-of-sequence questions then they will never get back on schedule.

So, here we can customize the presentation and try to satisfy your needs as we go along. It's not always possible to do this, but I'll try.

Quote:

Originally Posted by aijazbaig1

VHDL says that components are like chip connectors and nothing else. We actually have to link them to entity.

"We" don't link them; the compiler and/or simulator link them. If "we" use defaults for everything, "we" can get to a final solution without understanding everything. This works OK for simple examples, but for people trying to understand, it takes some work. (A little pun here for the VHDL literati: work. Get it? No? Oh, well...)

Quote:

Originally Posted by aijazbaig1

there isn't a single line which actually links component mux to entity mux. And then it goes on to instantiate a component called M1 based on that. Does it mean that if the names of the entity and the component are exactly the same then they get linked automatically??

That's a pretty good guess.

When an architecture is compiled, if it has a COMPONENT declaration (and no CONFIGURATION information), the compiler looks into the "work" library to see if an entity with that exact name has been previously compiled. If not, an error is generated, and the compilation fails. This is the default behavior.

Note that, at compile time, the compiler doesn't care about any architecture(s) of the component; it just needs to know the signal names and signal types and signal directions of everthing in that component's port.

If there is some configuration information (giving a library and component name and some configuration information, like "FOR ... USE libraryname.entityname(architecturename)", the compiler looks for a component with that name in that library. (Note that if you are going to give configuration information like this, there is no default library, and you must tell it to look in "work" if that's where it is.)

Now, at simulation time, we will simulate a particular entity/architecture, and as the design is loaded into the simulator, the linkage between the component entities of the design is established so that everything is "hooked up". At this time, if there are any missing architectures for any of the component entities, you get some kind of "load" error, and the simulator aborts. Certain kinds of inconsistencies in the architectures can cause load errors also, so that a design that was successfully compiled might actually have errors that aren't manifested until you try to simulate. See Footnote.

Quote:

Originally Posted by aijazbaig1

when we instantiate component(s) and we would like the ports of the component to get connected to external signals which could be the input/output ports of a higher level entity...do we have to place the port names of the entity at the corresponding component ports directly if we are using position based instantiation?

1. When you declare a component (a lower-level entity) at any level, the signals in the COMPONENT port declaration must have exactly the same names and types and directions as that component's ENTITY port that was previously compiled into the library.

2. This has nothing to do with the instantation, which can use whatever local signal names you use for feeding the component instance. (They could be the same or not.)

3. If you use position based instantiation, the local signal names in the port map must also be in the same order as the component declaration. (But the names of local variables don't have to be the same as the component's port declaration signals.)

4. If you are using some kind of block diagram editor or other GUI for creating the structural hierarchy, there may be some things that it does about forcing signal names to match pin names. They all have some little quirks. I will not be addressing such issues here. Here, all source consists of VHDL text files. Period.

Here's my design flow:

Before starting the design, write a complete Engineering Specification that describes Inputs, Processing and Outputs for the design. It doesn't have to be a complete functional specification (giving specifications of each and every module/component in the design), but should explicitly list these three main parts. If you don't have a specification, how will you know when you are done?

But seriously, in large organizations (or, maybe, in not-so-large organizations), sometimes one team starts to write a testbench from the specification and another team starts to implement the design, using the same specification. There is no communication between the teams unless one or the other perceives some inconsistencies in the specification, in which case they send it back to the Project Engineer for clarification. (The design team devises whatever simulation tests they need to exercise various parts of the design, but not necessarily as complete a test as is required before releasing the design to Manufacturing.)

0. Try to guess some overall structure that consists of a hierarchy of components that will make up the design. This will almost certainly change as the design is being implemented, but an overview is important before you write the first "LIBRARY ieee;" into your first entity/architecture source file.

1. Create and compile the lowest component(s) first

2. Copy/past the lower element's PORT(...); stuff into the COMPONENT PORT(...) stuff of the higher element(s), so that I know it's consistent. (It's easier when I go to proofread stuff as part of the debug process. The port declaration of the entity looks exactly like the port stuff in the component declaration.)

3. Instantiate component(s) in the higher element. Note that I personally never use position based instantiation. It's just too easy to get things wrong, and you always have to go back to the component declaration to make sure things are in the correct order. Why ask for trouble? There are enough ways to screw things up without deliberately developing habits that save a few keystrokes now but leave things ready to kill us later.

In cases where there is only one component (not the usual case), it's easy to make the local signal names exactly the same as the names on the port of the component, but, in general they won't be the same.

What if you instantiate two components of the same type? Not all signals connected to the two instances will be exactly the same, will they? That means that some local signal names will have to be different than the signals on the port of the component declaration. So: get used to it; deal with it.

So, my version of your example might look like this:

Code:

--
-- Note that my convention is to put VHDL pre-defined stuff
-- in caps and user stuff in lower-case.
--
-- VHDL is not case sensitive, so it really doesn't matter,
-- and some people do the exact opposite.
-- I like for the VHDL control stuff and other keywords
-- to really stand out in the listing (on-screen or printed).
--
-- I also like for the structure of the program to really
-- stand out in the listing. I use an indenting style similar
-- to that used by many C programmers, but, again, the compiler
-- doesn't care. The idea is that, whatever convention you
-- adopt, BE CONSISTENT. It really helps you when you go to
-- debugging (in the extremely rare cases when it doesn't work
-- perfectly the first time).
--
-- To each his/her own.
--
-- davekw7x
--
LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.ALL;

ENTITY mux IS
    PORT(a   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         b   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         sel : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
         c   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
END mux;

ARCHITECTURE example OF mux IS

--
-- Note that I always give processes a name. Sometimes
-- helps when debuggine, since we know where the simulator
-- is if (when) it bombs. Typically, I give it a name
-- related to a signal that is being driven
--
-- My processes are always named "gen_something", and I never
-- use "gen_anything" for signals or anything other than
-- a process label.
--
-- Instead of a string of IF.. ELSIF..END IF stuff, I
-- probably would have used something else, but the
-- following, from your example, is valid for simulation 
-- and synthesis, so I won't change it to my style just for the
-- heck of it.
--
BEGIN
   gen_c: PROCESS(a, b, sel)
   BEGIN
      IF (sel = "00") THEN
          c <= (OTHERS => '0');

      ELSIF (sel = "01") THEN
          c <= a;

      ELSIF (sel = "10") THEN
          c <= b;

      ELSE
          c <= (OTHERS => 'Z');

      END IF;
   END PROCESS gen_c;
END example;

--
-- Note that I always keep source code lines to fewer than 80 columns
-- so that I can get a decent printout that doesn't wrap lines arbitrarily.
--
-----------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

--
-- testbench entity has no port signals. It's all self-contained
--
ENTITY tb_mux IS
END ENTITY;

ARCHITECTURE testbench OF tb_mux IS

    -- note that I copy/pasted the PORT() from the mux entity's PORT()
    --
    COMPONENT mux
        PORT(a   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
             b   : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
             sel : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
             c   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
            );
    END COMPONENT;

--
-- My style is to declare components first and then do the local signals
-- but it doesn't matter to the compiler. It's just easier to add
-- new signals if the list of local signals is always in the same place
-- in the architecture.
--
    SIGNAL a,b,c : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL sel1  : STD_LOGIC_VECTOR(1 DOWNTO 0);



 BEGIN

   -- I always give an instance name somehow related to the
   -- name of the component. And I never use "i_anything" for
   -- signals or anything other than component instance names.
   -- (So that I don't absent-mindedly create some kind of name
   --  conflict.)
   --
   i_mux : mux 
   PORT MAP(a   => a,
            b   => b,
            sel => sel1,
            c   => c
           );

   gen_stimulus: PROCESS
   BEGIN

       a    <= X"11" AFTER 1 ns,
               x"AF" AFTER 2 ns,
               x"BB" AFTER 3 ns,
               x"6F" AFTER 4 ns;

       b    <= X"01" AFTER 1 ns,
               x"2F" AFTER 2 ns,
               x"3C" AFTER 3 ns,
               x"BE" AFTER 4 ns;

       sel1 <= "00" AFTER 1 ns,
               "01" AFTER 2 ns,
               "10" AFTER 3 ns,
               "11" AFTER 4 ns;
       WAIT;

    END PROCESS gen_stimulus;

END testbench;

Note that my comments give some clues as to my thought processes as I create and implement designs. I do not recommend that you change anything that you do just because I say, "that's the way I do it." Do things the way that seems best to you. In a class, the instructor may tell you specific ways of doing things (capitalization, naming, indentation, etc.). Sometimes you have to go along with the game, and express your individuality later.

Regards,

Dave

Footnote:
The same kind of thing could happen when you go to synthesize a design. It is possible for it to have been compiled (and, even, simulated) successfully but it could still have errors that keep it from being synthesized.

sabinqwe · #3 24-May-2008, 07:05

Hi everybody ..could someone help me with this??

port( A:in std_logic_vector (7 downto 0);
s:in std_logic_vector (2 downto 0);
yut std_logic);
end mux_8ch;
architecture model of mux_8ch is
begin
process(A,s)
begin
with s select y<=
A(0) when "000",
A(1) when "100",
A(2) when "010",
A(3) when "110",
A(4) when "001",
A(5) when "101",
A(6) when "011",
A(7) when "111";

end process;
end model;

And the errors are:

# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(13): Illegal sequential statement.
# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(13): Illegal sequential statement.
# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(12): Selected signal assignment covers only 8 out of 729 cases.
# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(23): VHDL Compiler exiting

davekw7x · #4 24-May-2008, 08:42

Quote:

Originally Posted by sabinqwe

..could someone help me...

And the errors are:

# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(13): Illegal sequential statement.

select is a concurrent statement not a sequential statement. It doesn't go inside a process.

Quote:

Originally Posted by sabinqwe

# ** Error: C:/Documents and Settings/hgf/Desktop/mux_8ch.vhd(12): Selected signal assignment covers only 8 out of 729 cases.

Your model didn't take into account the fact that IEEE Standard Logic signals can take on more values than just '0' or '1'.

For purposes of this model, you probably just want to set the output to 'X' if the inputs are not all '0' or '1'.

My version of the circuit that uses a SELECT statement might look like:

Code:

LIBRARY ieee;
USE     ieee.std_logic_1164.ALL;

ENTITY mux_8ch IS
  PORT (a : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
        s : IN  STD_LOGIC_VECTOR (2 DOWNTO 0);
        y : OUT STD_LOGIC
        );
END mux_8ch;

ARCHITECTURE select_model OF mux_8ch IS
BEGIN

  WITH s SELECT 
    y <= a(0) WHEN "000",
         a(1) WHEN "100",
         a(2) WHEN "010",
         a(3) WHEN "110",
         a(4) WHEN "001",
         a(5) WHEN "101",
         a(6) WHEN "011",
         a(7) WHEN "111",
         'X'  WHEN OTHERS;

END select_model;

Regards,

Dave

Footnote: Since this is a completely different topic than anything covered here, it would be appropriate to start a brand new thread rather than tacking a new question at the end of a thread that is almost two years old. Give your thread a meaningful title. The title would contain something about VHDL, and something about your specific problem. So the title of your new thread would be something like "VHDL Illegal Sequential Statement Error." Or, maybe "VHDL Question About SELECT Statement." Or some such thing.

davekw7x · #5 24-May-2008, 10:23

Quote:

Originally Posted by davekw7x

...

My version of the circuit that uses a SELECT statement might look like:

Actually, I was using your assignment convention. My design, if I used a SELECT statement, would probably be more like:

Code:

  WITH s SELECT 
    y <= a(0) WHEN "000",
         a(1) WHEN "001",
         a(2) WHEN "010",
         a(3) WHEN "011",
         a(4) WHEN "100",
         a(5) WHEN "101",
         a(6) WHEN "110",
         a(7) WHEN "111",
         'X'  WHEN OTHERS;

Regards,

Dave

counterbugs · #6 12-Jun-2008, 11:52

I have run into a similar problem guys.

I'm guessing its in the code.

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Confusion with component instantiations in VHDL

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